codigos vhdl

[_Keny_]

vas a hacer la alu? con GAL o PAL ?

haber si con esto te puedes dar una idea...

library ieee;
use ieee.std_logic_1164.all;

entity alu is port(
a,b: in std_logic_vector(3 downto 0);
sel: in std_logic_vector(2 downto 0);
c:out std_logic_vector(3 downto 0));
end alu;

architecture logica of alu is
begin
alu: process(a,b,sel)
begin
case sel is
when "001"=>c<= (a xor b);
when "010"=>c<= (a and b);
when "011"=>c<= (a or b);
when "100"=>c<= (a nor b);
when "101"=>c<= not(b);
when "110"=>c<= b;
when others=>c<="0000";
end case;
end process alu;
end logica;